1. Field of the Invention
The present invention relates in general to systems for generating integrated circuit (IC) layouts, and in particular to a method for determining where to position input/output (I/O) buffers and pads within an IC layout.
2. Description of Related Art
An IC designer typically employs synthesis tools to produce an IC design in the form of a gate level netlist referencing cells (circuit components) to be included in the IC and indicating which terminals of those cells are to be interconnected by nets (signal paths). The netlist also indicates which cell terminals are to transmit and receive the IC's input/output (I/O) signals. A cell library describes each kind of cell that may be included in the IC design, and the netlist indicates the nature of each cell by referencing an entry in the cell library for that particular type of cell.
While the netlist references cells to be included in the IC and indicates which of their terminals are to be interconnected, it does not indicate where each cell is to be placed or how it is to be oriented in a semiconductor and does not indicate how the nets interconnecting the cell terminals are to be routed. Therefore, after producing a gate level netlist, the IC designer typically employs a placement and routing (P&R) tool to produce a placement plan indicating how each cell referenced by the netlist is to be positioned and oriented in an IC layout, and to produce a routing plan indicating how the nets are to be routed between cell terminals. The P&R tool also designs the signal paths that are to link some of the cell terminals to I/O pads on the surface of the IC that are to act as the IC's points of connection to external circuits. The signal paths between the cells and the I/o pads not only include conductors, but also include I/O buying each of the IC's I/O signals.
FIG. 1 illustrates in block diagram form a circuit cell 1 formed within an IC 10 that may transmit an I/O signal to or receive an I/O signal from an external circuit via an I/O buffer 2, an I/O pad 3, and an external signal path 4 leading to the external circuit. Exposed on the upper surface of the IC 10, the conductive I/O pad 3 acts as a point of connection for signal path 4. External signal path 4 may include, for example, a conductive bond wire, a solder ball or a spring contact bonded to or contacting pad 3. Signal paths 5 and 6, formed by conductors and vias residing on and between conductive layers of the IC above the substrate, interconnect cell 1, I/O buffer 2 and I/O pad 3. I/O buffer 2 amplifies the unidirectional or bidirectional I/O signal passing between cell 1 and I/O pad 3.
FIG. 2 is a simplified plan view of a conventional layout for an IC 10 having a semiconductor substrate including a core area 12 containing the circuit cells and a peripheral area 14 surrounding the core area containing the I/O buffers. The IC's I/O pads typically reside above peripheral area 14. A grid of power and ground lines (not shown) usually delivers power to all of the cells forming the IC, and the cells are positioned within core area 12 in rows extending along the power and ground grid lines. Since the I/O buffers are typically larger and have greater power requirements than other cells of an IC, separate power and ground lines are provided in peripheral area 14 to deliver power to the I/O buffers. Each I/O buffer typically may occupy only a limited set of “legal positions” 16 along the power and ground lines within peripheral area 14. The I/O pads reside above the I/O buffers at the same set of legal positions 16.
As chip integration density and complexity within core area 12 continue to increase, the number of IC I/O signals have increased to the point where in many cases there are an insufficient number of legal positions in the peripheral area 14 of an IC to accommodate all of the IC's I/O buffers and pads. In accordance with more recently developed “area I/O buffer” technology as illustrated in FIG. 3, power and ground grids for supplying I/O buffers extend over the entire IC so that I/O buffers and pads may be placed in a large number of legal positions 16 distributed in a regular array over the entire IC 10 including core area 12 and peripheral area 14.
The IC designer usually selects a legal position 16 for each I/O pad of the IC. When a P&R tool generates the placement and routing plan for an IC, it first prepares a placement plan specifying positions of all cells that are to reside in core area 12, and then prepares a routing plan describing the nets that are to interconnect terminals of those cells. The P&R tool may adapt the placement and routing plans to provide an appropriate I/O buffer at each legal position 16 that the designer has indicated is to be occupied by an I/O pad, and to provide signal paths interconnecting the I/O buffers and pads to the cells that communicate though them.
Referring to FIGS. 1 and 3, in many cases it may be advantageous to assign an I/O buffer 2 and the I/O pad 3 to which it is be linked via conductor 6 to different legal positions 16. For example when the distance between cell 1 and I/O pad 3 is relatively large, positioning I/O buffer 2 at some legal position 16 between cell 1 and the legal position of I/O pad 3 may be required to reduce signal attenuation in signal path 5 to an acceptable level or to reduce the signal path delay between cell 1 and pad 3 to an acceptable level. The designer may also establish other criteria for the layout that could be affected by I/O buffer placement. For example the designer may want all I/O buffers amplifying high frequency I/O signals or handling I/O signals of a particular voltage to be restricted to particular areas of the IC regardless of the positions of the I/O pads to which they are connected.
Since the choice of legal position 16 for each I/O buffer can impact the ability of an IC to satisfy a set of criteria that are affected by I/O buffer position, what is needed is a computationally efficient method that a P&R tool may employ to determine how to assign each I/O buffer or pad to a legal position 16 in a way that optimally satisfies that set of criteria.